Cardinal NIC and Chip Multiprocessor
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Dec 1, 2021 - Verilog
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innovus
Here are 10 public repositories matching this topic...
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
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Jul 12, 2025 - Verilog
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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Jan 16, 2023 - Verilog
This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standard VLSI backend flow using Cadence EDA tools, covering synthesis, placement, routing, verification, and GDSII generation.
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Sep 15, 2025 - Verilog
An application using Cadence IC Package
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Feb 12, 2023 - Verilog
This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.
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Nov 25, 2024 - Verilog
ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.
rtl verilog cadence modus asic-design cadence-incisive cadence-conformal innovus cadence-xcelium rtl-gds genus-synthesis
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Nov 10, 2025 - Verilog
Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level
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Jul 16, 2023
Simulation, Logical and Physical Syntesis of the RISC-V Steel Core using Cadence EDA tools.
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Jan 15, 2025 - Verilog
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